Spatio-Temporal Characterization of Diurnal Noise in Superconducting Quantum Processors

1. Corrections from Version 1.3

This section documents errors in the previous version.

Root causes of errors in V1.3:

1. The 11.3× drift reduction would require 91% correction efficiency, not the stated 85%.
2. The 14% fidelity improvement is mathematically inconsistent with the stated error parameters.
3. The 40% QEC uptime claim used an undefined threshold and is not reproducible.
4. V1.3 presented simulated data as if it were experimental calibration data.

2. Introduction

Diurnal drift in superconducting quantum processors may arise from thermal, mechanical, or infrastructure-driven environmental variations [1, 2]. This study uses numerical simulation to investigate the potential magnitude of such effects and the benefits of phase-aware correction.

Scope: This is a simulation study. No experimental data were collected or analyzed.

3. Model

3.1 Temporal Phase

We define the normalized daily phase:

ϕ(t) := (t − t₀) / T_cycle mod 1 ∈ [0, 1)

where T_cycle = 86,400 s.

3.2 Spatial Thermal Lag

For qubit k at position (x_k, y_k) on the chip, the thermal lag is modeled as:

δ_k = δ_center − (δ_center − δ_edge) · d_k / d_max

where d_k is the distance from chip center and δ_edge ≈ 1.5h, δ_center ≈ 2.5h.

3.3 Error Model

The gate error rate follows:

ε_k(t) = ε⁽⁰⁾_k + A_k/2 (1 − cos(2πϕ(t) − δ_k))

3.4 Correction Model

With efficiency η:

ε^corr_k(t) = ε⁽⁰⁾_k + (1 − η)(A_k/2) (1 − cos(2πϕ(t) − δ_k))

The theoretical drift reduction is:

R = 1 / (1 − η)

For η = 0.85: R = 6.67×.

4. Simulation Configuration

5. Results

5.1 Frequency Drift Reduction

5.2 Gate Fidelity

5.3 Spatial Thermal Lag Distribution

6. Discussion

6.1 Comparison with V1.3 Claims

The simulated improvements are more modest than claimed in V1.3:

• Drift reduction: ∼6–7× vs 11.3× claimed
• Fidelity improvement: ∼2% vs 14% claimed
• QEC uptime: Not reliably quantifiable

These discrepancies indicate that V1.3 either used different (unstated) parameters or contained calculation errors.

6.2 Physical Interpretation

The spatial variation in thermal lag is physically plausible:

• Edge qubits are closer to thermal boundaries
• Heat diffuses from package periphery inward
• Center qubits experience delayed temperature response

However, the absolute values (1.5–2.5h) depend on cryostat design and have not been experimentally validated.

7. Limitations

1. Simulation only: No experimental data
2. Assumed parameters: A = 2.6% is an assumption, not a measurement
3. First-harmonic model: Higher harmonics may be present
4. Thermal lag model: The center-edge gradient is assumed, not measured
5. QEC threshold: Standard threshold (0.5%) may not apply to all codes

8. Conclusion

This simulation study demonstrates that phase-aware correction can provide meaningful benefits if diurnal modulation is present at significant levels (A ≳ 2%):

• Drift reduction: ∼6–7× (not 11×)
• Fidelity improvement: ∼2% (not 14%)
• Spatial lag varies as expected from thermal diffusion

Critical next step: Experimental characterization of actual diurnal modulation amplitude on real hardware.

Data Availability

Simulation code is available as supplementary material. This document supersedes V1.3 (DOI: 10.5281/zenodo.17900332).

References

• [1] P. V. Klimov et al., Fluctuations of energy-relaxation times in superconducting qubits, Phys. Rev. Lett. 121, 090502 (2018).
• [2] M. Carroll et al., Dynamics of superconducting qubit relaxation times, npj Quantum Inf. 8, 132 (2022).